The present invention relates generally to integrated circuits, and more particularly to integrated circuits that includes both low voltage and high voltage devices.
While many types of integrated circuits may be designed to operate with a single internal voltage, it is often desirable to provide a circuit that is capable of handling two or more different voltage levels. One such application can be integrated circuits that include circuit devices (e.g., transistors as well as passive circuit elements) that operate in the range of a typical power supply voltage, and circuit devices that operate at voltage magnitudes that are substantially greater than a typical power supply voltage. The former circuit devices are often referred to as xe2x80x9clow voltage devices,xe2x80x9d while the latter are often referred to as xe2x80x9chigh voltage devices.xe2x80x9d
While the inclusion of high and low voltage devices may have various applications, one particular useful application can be within integrated circuits that include programmable and/or erasable nonvolatile storage elements. In such devices, a program and/or erase operation may include the application of a relatively high potential to one or more nonvolatile storage elements.
Nonvolatile storage elements may take a variety of forms, including electrically erasable programmable read only memory (EEPROM) cells, as but one example. Such memory cells may be arranged to primarily provide a storage function, or may be part of a memory that is xe2x80x9cembeddedxe2x80x9d into an integrated circuit that can provide a more complicated function. One type of nonvolatile memory cell is a silicon-oxide-nitride-oxide-silicon (SONOS) type transistor. SONOS type transistors can have advantageous programming and/or erase properties, over other conventional approaches. For example, some SONOS type technologies may include lower programming and/or erase voltages than other nonvolatile technologies.
The various different devices described above (low voltage, high voltage and SONOS) can have particular manufacturing requirements. Accordingly, conventional approaches to manufacturing such devices have included specialized steps that can be difficult to implement. In particular, for high voltage insulated gate field effect transistors (IGFETs), it may be desirable to provide multiple source/drain implant steps, while at the same time maintaining a predetermined channel length.
While high voltage IGFET type transistors may be n-channel or p-channel type transistors, the formation of high voltage p-channel transistors can be more difficult due to the lower breakdown voltages of such devices.
To better understand transistor formation steps and various aspects of the disclosed embodiments, two conventional high voltage transistor fabrication methods will now be described.
Referring now to FIGS. 5A and 5B, a first conventional method for forming a high voltage IGFET is shown in a side cross sectional view. As shown in FIG. 5A, a transistor structure 500 may be formed on a substrate 502. A transistor structure 500 may include a conductive gate 504 formed on a gate insulator 506 with sidewall insulators 508-0 an 508-1 (also referred to as spacers) and top insulator 510. Low voltage source/drain regions 512-0 and 512-1 may be formed by a first ion implantation step that can use a conductive gate 504/top insulator 510 and sidewall insulators (508-0 an 508-1) as implant masks. The energy of implanted ions is typically low enough to prevent ions from penetrating into a transistor channel 514.
To provide more favorable high voltage characteristics, source/drain regions (512-0 and 512-1) may be subjected to a second xe2x80x9chighxe2x80x9d energy ion implantation step. A high energy implant step may implant ions with greater energy than ion implantation steps that form low voltage devices. However, such higher energy ions can have greater penetrating power, thus a conventional top insulator 510 and conductive gate 504 thickness may not be great enough to prevent high energy ions from being implanted into a channel region 514. To retain channel doping integrity, an additional implant mask may be formed over a transistor structure, as shown in FIG. 5B.
FIG. 5B shows a high energy implant mask 516 formed over a transistor structure 500. However, FIG. SB shows possible drawbacks to such an approach. In particular, a high energy implant mask 516 may be misaligned with respect to an underlying conductive gate 504 and top insulator 510. A resulting misalignment of high energy source/drain regions (518-0 and 518-1) with respect to low energy source/drain regions (512-0 and 512-1) can reduce the breakdown voltage of a high voltage device. Along these same lines, such a misalignment can effectively reduce the channel length of a transistor as a high energy source/drain region 518-0 can extend past a low energy source/drain region 512-0.
Thus, while the approach of FIGS. 5A and 5B may provide for longer transistor channel lengths, misalignment may occur.
A second conventional approach for forming a high voltage IGFET 600 is shown in a series of side cross sectional views in FIGS. 6A and 6B. FIG. 6A shows a substrate 602 on which may be formed a gate insulator layer 604, a conductive gate layer 606, and a top insulating layer 608. A gate etch mask 610, of photoresist or the like, may be formed over a top insulating layer 608. A gate etch mask 610 may have a desired gate shape.
As shown in FIG. 6B, layers (604-608) formed over a substrate may be etched with a gate etch mask 610. A resulting gate structure 600 may include a gate insulator 604, a conductive gate 606, and a top insulator 608. Following the formation of a gate structure 600, low energy source/drain regions 612 may be formed with a first implantation step. Further, high energy source/drain regions 614 may also be formed with a second implantation step having a higher energy than a first implantation step. A combination of a gate etch mask 610, top insulator 608, and conductive gate 606 can serve to prevent high energy implant ions from entering a channel region 616. Thus, low and high energy source/drain regions (612 and 614) can be self-aligned with a gate etch mask 610.
One drawback to an approach like that of FIGS. 6A and 6B can be limitations in transistor formation. More particularly, source/drain regions (612 and 614) can be aligned with edges of the gate. Thus, larger spacing between source/drain regions, such as that achieved in the example of FIGS. 5A and 5B, may not be possible with an approach such as that show in FIGS. 6A and 6B.
Another concern associated with high voltage devices can be current leakage. More particularly, if an ion implantation step results in the implantation of ions on the edge of an isolation region, it may be easier for a leakage path to develop through such isolation regions. This may be an important issue for devices that are formed with higher energy implant step due to the deeper penetration of high energy ion.
In light of the above, it would be desirable to arrive at some way of forming a high voltage device that may be easily integrated into an existing IGFET and/or SONOS manufacturing process. It would also be desirable to arrive at some way of forming a high voltage device that does not suffer from the drawbacks of the conventional approaches described above.
According to one embodiment of the present invention, a method of forming a semiconductor device may include implanting first ions into a low voltage (LV) region and a high voltage (HV) region of a substrate. A HV region may include a HV gate structure that includes insulating sidewalls, a top insulator, and a HV gate. Second ions may be implanted into a HV region to form high voltage source/drain regions. A top insulator of a HV gate structure may be exposed when second ions are implanted. A top insulator and insulating sidewalls may be implant masks for second ions, in a self-aligned high energy source/drain implant step.
According to one aspect of the embodiments, first and second ions may include boron and high voltage source/drains regions may be part of a p-channel high voltage transistor.
According to another aspect of the embodiments, first ions may be implanted with a low energy implant while second ions may be implanted with a high energy implant. A low energy may be less than 30 keV, while a high energy may be greater than 45 keV. Such differences in implant energy may form graded junctions having advantageously higher junction breakdown voltages.
According to another aspect of the embodiments, first ions may form low voltage source/drains in a LV region of a substrate. A LV region may include a LV gate structure that includes insulating sidewalls, a top insulator, and a LV gate. Thus, first ions may form LV source/drain regions, and at the same time form portions of graded HV source/drain regions.
According to another aspect of the embodiments, a third region of a substrate may include a nonvolatile gate structure. A nonvolatile gate structure may include insulating sidewalls, a top insulator, and a nonvolatile gate formed over a charge storing structure. A third region may be masked from first and second ions. Thus, an HV device that includes graded source and drain regions may be formed with nonvolatile devices.
According to another aspect of the embodiments, a nonvolatile gate structure charge storing structure may include a silicon nitride containing layer sandwiched between silicon dioxide containing layers. Such a charge storing structure may form SONOS type devices.
According to another aspect of the embodiments, a HV region may include implant mask structures. Implant mask structures may be formed with the same steps as a HV gate structure, but may be formed over an interface between an active area (e.g., an area that may contain a transistor source/channel/drain) and an isolation structure. Implant mask structures may prevent high energy ions from being implanted into such interfaces. Preventing high energy ions from being implanted into such regions may prevent current leakage paths from developing.
According to another aspect of the embodiments, a top insulator in a HV gate structure may be relatively thick, when compared with conventional approaches, to a gate length. For example, a gate length may be less than 0.5 microns, while a top insulator may be thicker than 2,200 angstroms.